library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dds4 is Port ( clock : in std_logic; daout : out std_logic_vector(5 downto 0)); end dds4; architecture behavioral of dds4 is signal romadrs: std_logic_vector (6 downto 0); signal latch : std_logic_vector (6 downto 0); subtype WAVE is STD_LOGIC_VECTOR (6 downto 0); type ROM is array (0 to 127) of WAVE; constant SINE : ROM := ( "1000000","1000011","1000110","1001001","1001100","1001111","1010010","1010101", "1011000","1011011","1011110","1100000","1100011","1100110","1101000","1101010", "1101101","1101111","1110001","1110011","1110100","1110110","1111000","1111001", "1111010","1111011","1111100","1111101","1111110","1111110","1111111","1111111", "1111111","1111111","1111111","1111110","1111110","1111101","1111100","1111011", "1111010","1111001","1111000","1110110","1110100","1110011","1110001","1101111", "1101101","1101010","1101000","1100110","1100011","1100000","1011110","1011011", "1011000","1010101","1010010","1001111","1001100","1001001","1000110","1000011", "1000000","0111101","0111010","0110111","0110100","0110001","0101110","0101011", "0101000","0100101","0100010","0100000","0011101","0011010","0011000","0010110", "0010011","0010001","0001111","0001101","0001100","0001010","0001000","0000111", "0000110","0000101","0000100","0000011","0000010","0000010","0000001","0000001", "0000001","0000001","0000001","0000010","0000010","0000011","0000100","0000101", "0000110","0000111","0001000","0001010","0001100","0001101","0001111","0010001", "0010011","0010110","0011000","0011010","0011101","0100000","0100010","0100101", "0101000","0101011","0101110","0110001","0110100","0110111","0111010","0111101" ); begin process (clock) begin if (clock' event and clock = '1') then romadrs <= romadrs + '1'; end if; end process; process (clock) begin if (clock' event and clock = '0') then latch <= SINE(CONV_INTEGER ( romadrs )); end if; daout <= latch(6 downto 1); end process; end behavioral;